Time is money. This is especially important in the development of modern electronics equipment. But until recently, all were forced to accept the fact that debugging ща firmware begins after completion of the design of hardware system. But with the development of the concept of virtual prototypingTechnologies Of Rapid Prototyping.. Read more ... » situation has changed cardinally.
Existing approaches to modeling of hardware SoC imply its description on the level of register transfer level (RTL), as a rule – on hardware description languages (HDL): VHDL or Verilog. RTL-models are a description of the equipment as a set of registers and the logical connections between them. The interaction between modules is detailed to descriptions of individual signals and conclusions. Naturally, RTL-models describe the equipment up to the cycle. In fact, RTL-description of digital integrated circuits – is a completed project of the scheme in generalized form, i.e. without reference to specific manufacturers VLSI libraries.
However, the use of RTL-models for the design and verification software is problematic because:
• Simulation speed is limited because HDL-simulator must handle many events associated with changes in the signals. This is at variance with the requirement of high speed of system simulation.
• Creation of RTL-model – is a very significant stage of development of the hardware part of the project, it is actually the final part of the circuitry works (thanks to modern CAD). It takes a lot of time and money. But with increasing complexity of equipment the beginning the process of joint verification of software and hardware of SoC is postponed to later stages of the design, that contradicts the requirements of minimizing development time.
The basis of “virtual prototyping” is a simple principle: it is necessary to create a behavioral model of the architecture prior to the detailed development of hardware and software. This virtual prototype should represent an exact behavioral model to cycle throughout the SoC, including the hardware and software part. The speed of processing of this model cannot be less than 100 thousand instructions per second that is much higher than for the RTL-descriptions. The model should be created at the earliest stage of design.
At first glance, the problem seems insoluble. But on the other hand, developers in verification should analyze up-cycle the processes of transfer between the blocks of data and instructions to identify points of commencement and duration of exchange, especially when the transfer time depends on the parameters of packets. In this analysis it would be superfluous to consider the formation of separate signals on the buses, because in terms of software the interaction with equipment is to exchange data packets with time parameters. Therefore, all events of switching signals can be replaced by a single event of reading or writing, called the transaction.
Moreover, several commands to read or write can be defined by one transaction, for example – to record data in consecutive memory locations. Since the speed of modeling is inversely proportional to the number of events, with a decrease in their intensity in the 100-1000 times the typical model of the level of transactions is performed in 100 times faster than corresponding RTL-model.
Thus, an effective way for the joint development and verification of software and hardware SoC – is modeling at the transaction level (TL). It is important that the TL-model of the system – its virtual prototype – after successful verification can serve as a benchmark for the remaining phases of VLSI design (instead of the descriptive specifications).
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